//分辨率模块
//640x480@60:25.2MHz(96:48:640:16:800|2:33:480:10:525)
//800x600@60:40MHz(128:88:800:40:1056|4:23:600:1:500)
//1024x768@60:65Mhz(136:160:1024:24:1344|6:29:768:3:806)
//1600x900@60:108Mhz(80:96:1600:24:1800|3:96:900:1:1000)
//1920x1080@60:148.5Mhz(44:148:1920:88:2200|5:36:1080:4:1125)
module vga_resolution # (
    parameter       H_DISP = 12'd1600,                  //行分辨率,行有效数据
    parameter       V_DISP = 12'd900,                   //场分辨率,场有效数据
    parameter       FPS    = 11'd60                     //帖率，刷新率
)
(
    input                           clk,                //输入时钟
    input                           rst_n,              //低电平复位信号

    output  reg     [12:0]          H_SYNC,             //行同步
    output  reg     [12:0]          H_BACK,             //行显示后沿
    output  reg     [12:0]          H_FRONT,            //行显示前沿
    output  reg     [12:0]          H_TOTAL,            //行扫描周期

    output  reg     [12:0]          V_SYNC,             //场同步
    output  reg     [12:0]          V_BACK,             //场显示后沿
    output  reg     [12:0]          V_FRONT,            //场显示前沿
    output  reg     [12:0]          V_TOTAL,            //场扫描周期

    output  reg                     vga_clk,            //VGA时钟频率
    output  	                    rst_n_w             //内部复位信号
);
	wire			vga_clk_25m;				//PLL分频得到的25MHz时钟
	wire			vga_clk_40m;				//PLL分频得到的40MHz时钟
	wire			vga_clk_65m;				//PLL分频得到的65MHz时钟
	wire			vga_clk_108m;				//PLL分频得到的108MHz时钟
	wire			vga_clk_148m;				//PLL分频得到的148MHz时钟
	wire			locked_w;					//PLL输出稳定信号

	//待PLL输出稳定之后，停止复位
	assign rst_n_w = rst_n && locked_w;
	
    always @ (*) begin
        if (H_DISP == 12'd640 && V_DISP == 12'd480 && FPS == 11'd60) begin
            //640x480@60:25.2MHz(96:48:640:16:800|2:33:480:10:525)
            H_SYNC      = 12'd96;
            H_BACK      = 12'd48;
            H_FRONT     = 12'd16;
            H_TOTAL     = 12'd800;

            V_SYNC      = 12'd2;
            V_BACK      = 12'd33;
            V_FRONT     = 12'd10;
            V_TOTAL     = 12'd525;
            
            vga_clk     = vga_clk_25m;
        end
        else if (H_DISP == 12'd800 && V_DISP == 12'd600 && FPS == 11'd60) begin
            //800x600@60:40MHz(128:88:800:40:1056|4:23:600:1:500)
            H_SYNC      = 12'd128;
            H_BACK      = 12'd88;
            H_FRONT     = 12'd40;
            H_TOTAL     = 12'd1056;

            V_SYNC      = 12'd4;
            V_BACK      = 12'd23;
            V_FRONT     = 12'd1;
            V_TOTAL     = 12'd500;
            
            vga_clk     = vga_clk_40m;
        end
        else if (H_DISP == 12'd1024 && V_DISP == 12'd768 && FPS == 11'd60) begin
            //1024x768@60:65Mhz(136:160:1024:24:1344|6:29:768:3:806)
            H_SYNC      = 12'd136;
            H_BACK      = 12'd160;
            H_FRONT     = 12'd24;
            H_TOTAL     = 12'd1344;

            V_SYNC      = 12'd6;
            V_BACK      = 12'd29;
            V_FRONT     = 12'd3;
            V_TOTAL     = 12'd806;
            
            vga_clk     = vga_clk_65m;
        end
        else if (H_DISP == 12'd1600 && V_DISP == 12'd900 && FPS == 11'd60) begin
            //1600x900@60:108Mhz(80:96:1600:24:1800|3:96:900:1:1000)
            H_SYNC      = 12'd80;
            H_BACK      = 12'd96;
            H_FRONT     = 12'd24;
            H_TOTAL     = 12'd1800;

            V_SYNC      = 12'd3;
            V_BACK      = 12'd96;
            V_FRONT     = 12'd1;
            V_TOTAL     = 12'd1000;
            
            vga_clk     = vga_clk_108m;
        end
        else if (H_DISP == 12'd1920 && V_DISP == 12'd1080 && FPS == 11'd60) begin
            //1920x1080@60:148.5Mhz(44:148:1920:88:2200|5:36:1080:4:1125)
            H_SYNC      = 12'd44;
            H_BACK      = 12'd148;
            H_FRONT     = 12'd88;
            H_TOTAL     = 12'd2200;

            V_SYNC      = 12'd5;
            V_BACK      = 12'd36;
            V_FRONT     = 12'd4;
            V_TOTAL     = 12'd1125;
            
            vga_clk     = vga_clk_148m;
        end
    end

	//时钟分频模块
	vga_pll u_vga_pll (
		.inclk0				(clk),
		.areset				(~rst_n),
		.c0					(vga_clk_25m),		//VGA时钟25MHz
		.c1					(vga_clk_40m),		//VGA时钟40MHz
		.c2					(vga_clk_65m),		//VGA时钟65MHz
		.c3					(vga_clk_108m),		//VGA时钟108MHz
		.c4					(vga_clk_148m),		//VGA时钟148MHz
		.locked				(locked_w)
	);

endmodule 
